Fabricating integrated circuits with faster and/or an increasing number of semiconductor devices is a continuing trend in integrated circuit technology. A very influential factor in this trend is technology scaling, i.e., the reduction in transistor feature sizes. Technology scaling has enabled transistors to become smaller, thus allowing for more dense integrated circuits in terms of the number of transistors packed on a chip.
Semiconductor devices are formed by performing a sequence of different processes on a semiconductor wafer. Some of these processes include doping, etching, oxidizing, or depositing various layers. Typically, only selected portions of the wafer are subjected to these processes at any given stage of fabrication.
The processing of selected portions of a semiconductor wafer can be accomplished using well known lithographic methods. In such methods, a photomask is used to transfer a desired pattern to the semiconductor wafer. The photomask may be a patterned chrome layer overlying a quartz substrate.
The pattern features of photomasks are becoming progressively smaller so as to keep up with the demand for more dense integrated circuits. These smaller pattern features are currently formed by a photomask fabrication method that employs electron-beam (e-beam) lithography, using positive or negative resists, dry etching and critical dimension scanning electron microscopy (CDSEM).
As is well known, the term critical dimension (CD) refers to the size of the smallest geometrical feature which can be formed during semiconductor device/circuit manufacturing using a given technology. The photomask fabrication method described above has many problems achieving CD uniformity requirements for 90 nanometer and smaller mask technology. Specifically, during e-beam lithography, local CD errors are induced by proximity effects, and global CD errors are caused by vacuum and heating effects. Global and local CD errors also occur during mask development and etching due to pattern loading differences and trench linearity problems. During CDSEM, where a negative resist has been used during e-beam lithography, the numerous non-conducting areas (the areas of the mask where the quartz substrate has been exposed by removal of the chrome layer) of the photomask become statically charged during handling, which causes CD measurement problems. The static charging also attracts dust and other particles to the photomask, which due to the high pattern density and the large size of the wafer dies, increases the probability of fatal defects in the individual wafers, thus resulting in lower process yields.
Accordingly, a photomask fabrication method is needed which is capable of achieving CD uniformity requirements of 90 nanometer or higher mask technology while eliminating or minimizing the above problems.